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Mohammad Alian
Assistant Professor
offices : 2022 Eaton Hall, 253 Nichols Hall |
Biography
Mohammad Alian is an Assistant Professor at the EECS department of the University of Kansas. Before joining KU, he completed his Ph.D. and MS at UIUC and UW-Madison, respectively. At UIUC, he developed dist-gem5 and MCN. dist-gem5 is part of the official gem5 release and MCN is the precursor to the development of Samsung's AxDIMM. His team at KU got second place Samsung open innovation contest for AxDIMM technology. Four best paper candidacies have recognized his research in top computer architecture conferences, including MICRO 2018 and HPCA 2017, and an honorable mention in IEEE Micro Top Picks 2017. He is a co-PIs of the SRC/DARPA JUMP 2.0 ACE Center for Evolvable Computing aiming at transforming the distributed computing of the next decade. Mohammad's research explores opportunities in the intersection of computer architecture and networking to shape the future of data centeric computing.
News
- 03/22/2023 Received an NSF CAREER award for research on near-memory datacenter network!
- 02/28/2023 gem5 profiling accepted to ISPASS 2023!
- 02/24/2023 Neel and Johnson presenting their research in YArch and FireSim workshops hold in conjunction w/ ASPLOS!
- 02/12/2023 I am visiting EPFL PARSA Lab for one semester!
- 01/27/2023 Check out our latest addition to gem5! DPDK on gem5 is open source!
- 01/05/2023 Official announcement of the ACE Center for Evolvable Computing, funded by a $31.5 million grant from JUMP 2.0!
- 09/21/2022 Serving as travel grant chair on ISPASS 2023!
- 09/07/2022 Serving on ISCA 2023 ERC!
- 09/01/2022 Johnson is presenting a poster at ACM Student Research Competition in MICRO!
- 08/30/2022 Our team got second place in Open Innovation Contest for AXDIMM Technology
- 07/19/2022 IDIO got accepted to MICRO 2022!
- 07/15/2022 Presenting our recent research at Intel Labs!
- 07/08/2022 "CCRI: Planning-C: Accelerated Infrastructure for Simulating Future Systems" is selected for funding by NSF!
- 06/03/2022 Neel Patel received SFS scholarship. Congrats Neel!
- 03/10/2022 Two BlueField2 DPUs donated by NVIDIA!
- 12/15/2021 Our proposal is selected as one of the finalist in Open Innovation Contest for AXDIMM Technology!
- 08/01/2021 Samsung Grant!
More
Research
Areas of interest: Computer Architecture and Systems
Vision: The computation in future datacenters will be distributed over a heterogenous array of processing elements, packaged modularly within a server's boundaries. The inter- and intra-server data movement will bottleneck such a computing landscape. The vision of my research is to seamlessly integrate processor, memory, and network architecture through a co-design with operating systems, network software stack, and software libraries to minimize the data movement in future datacenters.
My current research focus is on the following four thrusts:
I have several open Ph.D. positions and one postdoc position. Please contact me if you are interested in working on the following projects!
Intelligent I/O Data Steering at Scale
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The data delivery between I/O devices is often managed by the CPU, using an intermediate ring buffer inside DRAM. Therefore, high-bandwidth I/O devices — such as modern network interface cards (NICs) — impose immense pressure on the server's memory subsystem. To alleviate this pressure, modern CPUs support Direct Cache Access (DCA) technology to directly place I/O data in the last-level cache (LLC). The intersection of several trends, such as the deployment of ultra-high-bandwidth NICs in datacenters, non-inclusive cache hierarchies, and novel IaaS programming paradigms, calls for re-examining the DCA technology and management policies. Related Publications: ISPASS'20, CAL'20, ISCA'21, MICRO'22, +1 in baking |
IDIO Architecture, MICRO'22
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Near-Data Processing at Scale
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Data movement is the primary performance and energy bottleneck in today's and the future computing landscape. Near-data processing has the potential to alleviate this bottleneck and enable the best of CMOS technology.
However, practical near-data processing architectures products need to resolve the following challenges: cache coherency, memory consistency, virtual address translation, concurrent host and NDP accesses, data mapping programmability, precise exception, and efficient notification of completion mechanism. In this research thrust, we aim to develop near-data processing architectures that resolve the above challenges.
Related Publications: MICRO'18, MICRO'19, +2 under submission, +1 in baking |
Memory Channel Network (MCN), MICRO'18
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Communication Specialization at Scale
Architectural Simulation at Scale
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Software-based simulation is the backbone of computer architecture research and development. Architectural simulators such as gem5 are widely used by academia and industry for modeling different aspects of future computing platforms. However, traditionally, the focus of architectural simulators was on just simulating CPU and memory sub-systems, ignoring the I/O subsystem and the complex interplay between software/OS/hardware and network. Identifying the need for a fast, accurate, and detailed full-system simulation of future large-scale systems, we strive to extend state-of-the-art architectural simulators to model modern network technologies and run the latest software stack. Another important challenge in architectural simulation is the steep learning curve of such simulators. Our latest support from NSF targets this challenge.
Related Publications: ISPASS'17, IISWC'18, ISPASS'20, arXiv'20, +2 under submission, +1 in baking |
dist-gem5, ISPASS'17
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Selected Publications
For the full list please visit my google scholar
- Johnson Umeike, Neel Patel, Alex Manley, Amin Mamandipoor, Heechul Yun, Mohammad Alian, "Profiling gem5 Simulator," ISPASS 2023 [paper][slides]
- Siddharth Agarwal, Minwoo Lee, Ren Wang, Mohammad Alian, "Enabling Kernel Bypass Networking on gem5," Arxiv 2023 [paper][ open source]
- Mohammad Alian, Siddharth Agarwal, Jongmin Shin, Neel Patel, Yifan Yuan, Daehoon Kim, Ren Wang, Nam Sung Kim, "IDIO: Network-driven, inbound network data orchestration on server processors," MICRO 2022 [paper][slides]
- Ki-Dong Kang, Gyeongseo Park, Hyosang Kim, Mohammad Alian, Nam Sung Kim, and Daehoon Kim, "NMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads," MICRO 2021 [paper]
- Yifan Yuan, Mohammad Alian, Yipeng Wang, Ilia Kurakin, Ren Wang, Charlie Tai, Nam Sung Kim, "Don't Forget the I/O When Allocating Your LLC," ISCA 2021 [technology adapted by Intel®] [paper][slides]
- Mohammad Alian, Jongmin Shin, Ki-Dong Kang, Ren Wang, Alexandros Daglis, Daehoon Kim, Nam Sung Kim, "IDIO: Orchestrating Inbound Network Data on Server Processors," IEEE Computer Architecture Letters (CAL) 2020 [paper]
- Soroush Ghodrati, Byung Hoon Ahn, Joon Kyung Kim, Sean Kinzer, Brahmendra Yatham, Navateja Alla, Hardik Sharma, Mohammad Alian, Eiman Ebrahimi, Nam Sung Kim, Cliff Young, Hadi Esmaeilzadeh, "Planaria: Dynamic architecture fission for spatial multi-tenant acceleration of deep neural networks," MICRO 2020 [paper][slides]
- Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, et al. "The gem5 simulator: Version 20.0+," arXiv preprint 2020 [paper]
- Mohammad Alian, Yifan Yuan, Jie Zhang, Ren Wang, Myoungsoo Jung, and Nam Sung Kim, "Data direct I/O characterization for future I/O system exploration," ISPASS 2020 [paper][slides]
- Mohammad Alian, and Nam Sung Kim, "NetDIMM: Low-latency, near-memory network interface architecture," MICRO 2019 [paper][slides]
- Mohammad Alian, Seung Won Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam McPadden, Oliver OHalloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-mei Hwu, and Nam Sung Kim, "Application-transparent near-memory processing architecture with memory vhannel network," MICRO 2018 [best paper nominee][industry product] [paper][slides]
- Youjie Li, Jongsea Park, Mohammad Alian, Yifan Yuan, Qu Zheng, Petian Pan, Ren Wang, Alexander Gerhard Schwing, Hadi Esmaeilzadeh, and Nam Sung Kim, "A network-centric hardware/argorithm co-design to accelerate distributed training of deep neural networks," MICRO 2018 [hardware prototype demonstration] [paper][slides]
- Mohammad Alian, Krishna Parasuram Srinivasan, and Nam Sung Kim, "Simulating PCI-Express interconnect for future system exploration," IISWC 2018 [best paper nominee] [paper][slides]
- Mohammad Alian, Gabor Dozsa, Umur Darbaz, Stephan Diestelhorst, Daehoon Kim, and Nam Sung Kim, "dist-gem5: Distributed simulation of computer clusters," ISPASS 2017 [best paper nominee][open source] [paper][slides]
- Mohammad Alian, Ahmed Abulila, Lokesh Jindal, Daehoon Kim, and Nam Sung Kim, "NCAP: Network-driven, packet context-aware power management for client-server architecture," HPCA 2017 [best paper nominee][IEEE Micro honerable mention] [paper][slides]
Current Students
- Amin MamandiPoor, Ph.D. (Expected 2026)
- Johnson Umeike, Ph.D. (Expected 2027)
- Siddharth Agarwal, Ph.D. (co-advised w/ Prof. Nam Sung Kim at UIUC)
- Ramesh Ganapam, Ph.D. (Expected 2028)
- Neel Maulik Patel, MS.
- Derrick Quinn, MS.
- Alex Manley, MS.
- Minwoo Lee, Undergrad
- Luke Staudacher, Undergrad
Teaching
- EECS-700 Special Topics on Modern Computer Architecture & Design: Spring 2021, Fall 2022
- EECS-645 Computer Architecture: Spring 2022
- EECS-388 Embedded Systems: Fall 2020, Fall 2021 Fall 2022
Tools
Research Sponsors
- National Science Foundation
- Semiconductor Research Corporation
- Samsung Electronics
- NVIDIA (Equipment Donation)
- Ampere Computing (Equipment Donation)