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Mohammad Alian

Assistant Professor
Department of Electrical Engineering and Computer Science
University of Kansas

offices : 2022 Eaton Hall, 253 Nichols Hall
email : alian@ku.edu
links : Google Scholar | Curriculum Vitae

Biography

Mohammad Alian is an Assistant Professor at the EECS department of the University of Kansas. Before joining KU, he completed his Ph.D. and MS at UIUC and UW-Madison, respectively. At UIUC, he developed dist-gem5 and MCN. dist-gem5 is part of the official gem5 release and MCN is the precursor to the development of Samsung's AxDIMM. His team recently got second place Samsung open innovation contest for AxDIMM technology. Four best paper candidacies have recognized his research in top computer architecture conferences, including MICRO 2018 and HPCA 2017, and an honorable mention in IEEE Micro Top Picks 2017. Mohammad's research explores opportunities in the intersection of computer architecture and networking to build efficient datacenters.

News

Research

The main theme of my research is to attack the data movement bottleneck at hyper-scale computers through a co-design of computer architecture, operating systems, and networking. My current research focus is on the following four thrusts:

I have several open Ph.D. positions and one postdoc position. Please contact me if you are interested in working on the following projects!

Intelligent I/O Data Steering at Scale

The data delivery between I/O devices is often managed by the CPU, using an intermediate ring buffer inside DRAM. Therefore, high-bandwidth I/O devices such as modern network interface cards (NICs) impose immense pressure on the server's memory subsystem. To alleviate this pressure, modern CPUs support Direct Cache Access (DCA) technology to directly place I/O data in the last-level cache (LLC). The intersection of several trends, such as the deployment of ultra-high-bandwidth NICs in datacenters, non-inclusive cache hierarchies, and novel IaaS programming paradigms, calls for re-examining the DCA technology and management policies.

Related Publications: ISPASS'20, CAL'20, ISCA'21, MICRO'22, +1 in baking

ddio IDIO Architecture, MICRO'22

Near-Data Processing at Scale

Data movement is the primary performance and energy bottleneck in today's and the future computing landscape. Near-data processing has the potential to alleviate this bottleneck and enable the best of CMOS technology. However, practical near-data processing architectures products need to resolve the following challenges: cache coherency, memory consistency, virtual address translation, concurrent host and NDP accesses, data mapping programmability, precise exception, and efficient notification of completion mechanism. In this research thrust, we aim to develop near-data processing architectures that resolve the above challenges.

Related Publications: MICRO'18, MICRO'19, +2 under submission, +1 in baking

mcn Memory Channel Network (MCN), MICRO'18

Architectural Simulation at Scale

Software-based simulation is the backbone of computer architecture research and development. Architectural simulators such as gem5 are widely used by academia and industry for modeling different aspects of future computing platforms. However, traditionally, the focus of architectural simulators was on just simulating CPU and memory sub-systems, ignoring the I/O subsystem and the complex interplay between software/OS/hardware and network. Identifying the need for a fast, accurate, and detailed full-system simulation of future large-scale systems, we strive to extend state-of-the-art architectural simulators to model modern network technologies and run the latest software stack. Another important challenge in architectural simulation is the steep learning curve of such simulators. Our latest support from NSF targets this challenge.

Related Publications: ISPASS'17, IISWC'18, ISPASS'20, arXiv'20, +2 under submission, +1 in baking

dist-gem5 dist-gem5, ISPASS'17

Selected Publications

For the full list please visit my google scholar

  • Mohammad Alian, Siddharth Agarwal, Jongmin Shin, Neel Patel, Yifan Yuan, Daehoon Kim, Ren Wang, Nam Sung Kim, "IDIO: Network-driven, inbound network data orchestration on server processors," MICRO 2022 [paper][slides]
  • Nedasadat Taheri, Alex Manley, Ahmni R Pang-Johnson, Mohammad Alian, "Profiling an Architectural Simulator," ISPASS 2022 [paper]
  • Ki-Dong Kang, Gyeongseo Park, Hyosang Kim, Mohammad Alian, Nam Sung Kim, and Daehoon Kim, "NMAP: Power Management Based on Network Packet Processing Mode Transition for Latency-Critical Workloads," MICRO 2021 [paper]
  • Yifan Yuan, Mohammad Alian, Yipeng Wang, Ilia Kurakin, Ren Wang, Charlie Tai, Nam Sung Kim, "Don't Forget the I/O When Allocating Your LLC," ISCA 2021 [technology adapted by Intel®] [paper][slides]
  • Mohammad Alian, Jongmin Shin, Ki-Dong Kang, Ren Wang, Alexandros Daglis, Daehoon Kim, Nam Sung Kim, "IDIO: Orchestrating Inbound Network Data on Server Processors," IEEE Computer Architecture Letters (CAL) 2020 [paper]
  • Soroush Ghodrati, Byung Hoon Ahn, Joon Kyung Kim, Sean Kinzer, Brahmendra Yatham, Navateja Alla, Hardik Sharma, Mohammad Alian, Eiman Ebrahimi, Nam Sung Kim, Cliff Young, Hadi Esmaeilzadeh, "Planaria: Dynamic architecture fission for spatial multi-tenant acceleration of deep neural networks," MICRO 2020 [paper][slides]
  • Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, et al. "The gem5 simulator: Version 20.0+," arXiv preprint 2020 [paper]
  • Mohammad Alian, Yifan Yuan, Jie Zhang, Ren Wang, Myoungsoo Jung, and Nam Sung Kim, "Data direct I/O characterization for future I/O system exploration," ISPASS 2020 [paper][slides]
  • Mohammad Alian, and Nam Sung Kim, "NetDIMM: Low-latency, near-memory network interface architecture," MICRO 2019 [paper][slides]
  • Mohammad Alian, Seung Won Min, Hadi Asgharimoghaddam, Ashutosh Dhar, Dong Kai Wang, Thomas Roewer, Adam McPadden, Oliver OHalloran, Deming Chen, Jinjun Xiong, Daehoon Kim, Wen-mei Hwu, and Nam Sung Kim, "Application-transparent near-memory processing architecture with memory vhannel network," MICRO 2018 [best paper nominee][industry product] [paper][slides]
  • Youjie Li, Jongsea Park, Mohammad Alian, Yifan Yuan, Qu Zheng, Petian Pan, Ren Wang, Alexander Gerhard Schwing, Hadi Esmaeilzadeh, and Nam Sung Kim, "A network-centric hardware/argorithm co-design to accelerate distributed training of deep neural networks," MICRO 2018 [hardware prototype demonstration] [paper][slides]
  • Mohammad Alian, Krishna Parasuram Srinivasan, and Nam Sung Kim, "Simulating PCI-Express interconnect for future system exploration," IISWC 2018 [best paper nominee] [paper][slides]
  • Mohammad Alian, Gabor Dozsa, Umur Darbaz, Stephan Diestelhorst, Daehoon Kim, and Nam Sung Kim, "dist-gem5: Distributed simulation of computer clusters," ISPASS 2017 [best paper nominee][open source] [paper][slides]
  • Mohammad Alian, Ahmed Abulila, Lokesh Jindal, Daehoon Kim, and Nam Sung Kim, "NCAP: Network-driven, packet context-aware power management for client-server architecture," HPCA 2017 [best paper nominee][IEEE Micro honerable mention] [paper][slides]

Current Students

Teaching

Research Sponsors

  • National Science Foundation
  • Semiconductor Research Corporation
  • Samsung Electronics
  • NVIDIA (Equipment Donation)